The present invention relates generally to semiconductor processing, and in particular to lithographic processes and lithography systems.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these higher device densities there have been, and continue to be, efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish higher device densities, smaller and smaller features sizes are required. These may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and surface geometry of corners and edges of various features.
High resolution lithographic processes are used to achieve small features. In general, lithography refers to processes for pattern transfer between various media. In lithography for integrated circuit fabrication, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist. The film is selectively exposed with radiation (such as optical light, x-rays, or an electron beam) through an intervening master template, the mask, forming a particular pattern. Exposed areas of the coating become either more or less soluble than the unexposed areas (depending on the type of coating) in a particular solvent developer. The more soluble areas are removed with the developer in a developing step. The less soluble areas remain on the silicon wafer forming a patterned coating. The pattern corresponds to the image of the mask or its negative. The patterned resist is used in further processing of the silicon wafer.
Critical dimensions of the patterned resist, such as line widths, affect the performance of the finished product and are sensitive to processing conditions. Processing conditions that affect critical dimensions include conditions relating to resist application, pre-baking, resist exposure, post-baking, and resist development. A few degrees variation in the pre-bake temperature, for example, can have a significant affect on critical dimensions. Many of the conditions that affect critical dimensions are difficult to control, often resulting in variations from batch to batch.
One way to deal with these variations is to adapt latter processing steps to compensate for variations that take place during earlier processing steps. In particular, feed-forward control based on measuring a critical dimension of the pattern that is latent within the resist after exposure, but prior to post-exposure baking and developing, has been suggested. This approach, however, is not entirely effective; the solubility of the resist, which defines the latent pattern, undergoes a smooth transition at pattern borders. Therefore, measurements of critical dimensions in latent patterns are imprecise and have a degree of subjectivity. Consequently, there remains an unsatisfied need for a lithographic process that provides effective adaptation of processing conditions to control critical dimensions in the patterned resist.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides lithographic systems and lithographic processes in which conditions affecting critical dimensions are controlled based on a latent image signature. The latent image signature characterizes the latent pattern present in a resist coating after selective exposure of the resist to actinic radiation. The latent image signature is determined from the full latent pattern within a region of the resist. Conditions for subsequent processing steps (feed forward control) and/or prior processing steps (feed back control) to produce desired critical dimensions are determined from the latent image signature. In another aspect of the invention the latent pattern is logically divided into a plurality of regions. Within each region, a characteristic of the latent pattern is analyzed to determine conditions to apply to that region during previous and/or subsequent processing steps. These conditions include a condition such as post-exposure baking temperature or developing temperature that can be separately controlled for each region. Region to region variations in pattern development can thereby be corrected. The systems and processes of the invention allow more effective control of critical dimensions than prior art processes that rely on a single critical dimension measurement made on a latent pattern.
One aspect of the present invention provides a lithography system comprising a lighting system for illuminating a substrate coated with a resist having a latent pattern, an imaging system for imaging the latent pattern to produce image data, a resist processing system, and a controller, wherein the controller regulates the resist processing system based on a parameter characteristic of the latent pattern and derived from the image data.
Another aspect of the present invention provides a lithography system, comprising means for determining a latent image signature for a latent pattern in a resist coating and means for regulating a resist processing condition based on the latent image signature.
A further aspect of the present invention provides a lithographic process comprising forming a resist coating over a substrate, selectively exposing the resist to actinic radiation to form a latent pattern within the resist coating, determining a latent image signature for the latent pattern, and post-baking, where appropriate, and developing the resist employing a condition determined based at least in part on the latent image signature.
A further aspect of the present invention provides a lithographic process comprising forming a resist coating over a substrate, selectively exposing the resist to actinic radiation to form a latent pattern within the resist coating, logically dividing the latent pattern into a plurality of portions, for each of the plurality of portions of the latent pattern, determining a parameter relating to the latent pattern, and post-baking, where appropriate, and developing the resist employing a condition that varies over the plurality of portions of the latent pattern based, at least in part, on the parameter relating to the latent pattern.
The invention extends to features hereinafter fully described and features particularly pointed out in the claims. The following detailed description and the annexed drawings set forth in detail certain illustrative examples of the invention. These examples are indicative of but a few of the various ways in which the principles of the invention may be employed. Other ways in which the principles of the invention may be employed and other objects, advantages and novel features of the invention will be apparent from the detailed description of the invention when consider in conjunction with the drawings.